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C HAPTER 4: P LACE AND R OUTE
A NALYZING F ITTING R ESULTS
Figure 3. Chip Planner
Resource usage in the Chip Planner is color coded. Different colors represent
different resources, such as unassigned and assigned pins and logic cells,
unrouted items, and row FastTrack ? fan-outs. The Chip Planner also allows
you to customize the floorplan view using filters to show pins and the
interior structure of the device.
To edit assignments in the Chip Planner, you can click a resource assignment
and drag it to a new location. You can use rubberbanding to display a visual
representation of the number of routing resources affected by the move.
A LTERA C ORPORATION
I NTRODUCTION TO THE Q UARTUS II S OFTWARE
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相关PDF资料
SW-QUARTUS-SE-FLT SUBSCRIPTION FLOATALL REPL
SW006012 C COMPILER FOR DSPIC30F FAMILY
SW006013 C COMPILER MPLAB FOR DSPIC DSC
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SW300003-EVAL LIBRARY SOFT MODEM-EVAL ONLY
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SW300060-EVAL LIBRARY ACOUSTIC ECHO-EVAL ONLY
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